iPEM

2.4 Gb SDRAM-DDR2

AS4DDR232M72APBG

AS4DDR232M72APBG

Rev. 1.1 12/12

5

Micross Components reserves the right to change products or specifications without notice.

following two sets of conditions (A or B) must be met to

obtainastablesupplystate(stablesupplydefinedas

V

minimum and maximum values as stated in Table20);

A. (single power source) The V

300mV to V

200ms; during the V

(when V

specificationsapply.

• V

converter output

• V

• V

time

• V

B. (multiple power sources) V

maintained during supply voltage ramping, for both

AC and DC levels, until supply voltage ramping

completes (V

voltagerampingiscomplete,Table20specifications

apply.

• Apply V

V

from when V

• ApplyV

V

achieved to when V

<500ms; while V

supplied from V

• VREF must track VCCQ/2, VREF must be within

time; V

• ApplyV

V

must be no greater than 500ms

2. For a minimum of 200

(CK, CK#), apply NOP or DESELECT commands and

take CKE HIGH.

3. Wait a minimum of 400ns, then issue a

PRECHARGE ALL command.

4. Issue an LOAD MODE command to the EMR(2). (To

issue an EMR(2) command, provide LOW to BA0,

provide HIGH to BA1.)

5. Issue a LOAD MODE command to the EMR(3). (To

issue an EMR(3) command, provide HIGH to BA0 and

BA1.)

6. Issue an LOAD MODE command to the EMR to enable

DLL. To issue a DLL ENABLE command, provide LOW

to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and

E9 can be set to “0” or “1”; Micron recommends setting

them to “0”.

7. Issue a LOAD MODE command for DLL RESET. 200

cycles of clock input is required to lock the DLL. (To

issue a DLL RESET, provide HIGH to A8 and provide

LOW to BA1, and BA0.) CKE must be HIGH the entire

time.

8. Issue PRECHARGE ALL command.

9. Issue two or more REFRESH commands, followed

by a dummy WRITE.