BLUENRG-132 datasheet(5/173 Pages) STMICROELECTRONICS

Part #	BLUENRG-132

Description	Bluetooth low energy wireless system-on-chip

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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BlueNRG-1

List of tables

DocID028866 Rev 1

5/173

List of tables

Table 1: Device summary table ..................................................................................................................1

Table 2: Interrupt vectors ..........................................................................................................................15

Table 3: Relationship between BlueNRG-1 states and functional blocks ................................................17

Table 4: SYSTEM_CTRL registers ...........................................................................................................18

Table 5: SYSTEM_CTRL - WKP_IO_IS register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x00 ......................................................................................................18

Table 6: SYSTEM_CTRL - WKP_IO_IE register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x04 ......................................................................................................19

Table 7: SYSTEM_CTRL - CTRL register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x08 ......................................................................................................19

Table 8: AHBUPCONV registers ..............................................................................................................19

Table 9: BLUE_CTRL registers ................................................................................................................19

Table 10: CKGEN_SOC registers ............................................................................................................23

Table 11: CKGEN_SOC - CONTROL register description: address offset

CKGEN_SOC_BASE_ADDR+0x00 .........................................................................................................23

Table 12: CKGEN_SOC - REASON_RST register description: address offset

CKGEN_SOC_BASE_ADDR+0x08 .........................................................................................................24

Table 13: CKGEN_SOC - DIE_ID register description: address offset

CKGEN_SOC_BASE_ADDR+0x1C .........................................................................................................24

Table 14: CKGEN_SOC - CLOCK_EN register description: address offset

CKGEN_SOC_BASE_ADDR+0x20 .........................................................................................................24

Table 15: CKGEN_SOC - DMA_CONFIG register description: address offset

CKGEN_SOC_BASE_ADDR+0x24 .........................................................................................................25

Table 16: CKGEN_BLE registers .............................................................................................................25

Table 17: CKGEN_BLE - REASON_RST register description: address offset

CKGEN_BLE_BASE_ADDR+0x08 ..........................................................................................................25

Table 18: CKGEN_BLE - CLK32K_COUNT register description: address offset

CKGEN_BLE_BASE_ADDR+0x0C ..........................................................................................................26

Table 19: CKGEN_BLE - CLK32K_PERIOD register description: address offset

CKGEN_BLE_BASE_ADDR+0x10 ..........................................................................................................26

Table 20: CKGEN_BLE - CLK32K_FREQ register description: address offset

CKGEN_BLE_BASE_ADDR+0x14 ..........................................................................................................26

Table 21: CKGEN_BLE - CLK32K_IT register description: address offset

CKGEN_BLE_BASE_ADDR+0x18 ..........................................................................................................26

Table 22: ADC channels ...........................................................................................................................27

Table 23: ADC data rate ...........................................................................................................................28

Table 24: ADC data rate with microphone mode......................................................................................28

Table 25: ADC registers............................................................................................................................30

Table 26: ADC - CTRL register description: address offset ADC_BASE_ADDR+0x00 ...........................30

Table 27: ADC - CONF register description: address offset ADC_BASE_ADDR+0x04 ..........................31

Table 28: ADC - IRQSTAT register description: address offset ADC_BASE_ADDR+0x08.....................32

Table 29: ADC - IRQMASK register description: address offset ADC_BASE_ADDR+0x0C ...................33

Table 30: ADC - DATA_CONV register description: address offset ADC_BASE_ADDR+0x14 ..............33

Table 31: ADC - OFFSET register description: address offset ADC_BASE_ADDR+0x18 ......................33

Table 32: ADC - SR_REG register description: address offset ADC_BASE_ADDR+0x20 .....................33

Table 33: ADC - THRESHOLD_HI register description: address offset ADC_BASE_ADDR+0x24 ........34

Table 34: ADC - THRESHOLD_LO register description: address offset ADC_BASE_ADDR+0x28 .......34

Table 35: Programmable data width and endian behavior (when bits PINC = MINC = 1) .......................37

Table 36: DMA interrupt requests .............................................................................................................40

Table 37: DMA registers ...........................................................................................................................41

Table 38: DMA - ISR register description: address offset DMA_BASE_ADDR+0x00 .............................41

Table 39: DMA - IFCR register description: address offset DMA_BASE_ADDR+0x04 ...........................45

Table 40: DMA_CHx registers ..................................................................................................................47

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