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AS8FLC2M32 Datasheet(PDF) 9 Page - Micross Components |
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AS8FLC2M32 Datasheet(HTML) 9 Page - Micross Components |
9 / 29 page FLASH AS8FLC2M32 AS8FLC2M32B Rev. 1.6 05/11 Micross Components reserves the right to change products or specifications without notice. 9 Temporary Sector Unprotect This feature allows temporary un-protection of previously protected sectors to change data in-system. Setting the RESET\ pin to VID activates the sector Unprotect mode. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET\ pin, all the previously protected sectors are protected again. The diagram below depicts the algorithm flow for this operation. Temporary Sector Unprotect Diagram Hardware Data Protection The command sequence requirements of UNLOCK cycles for PROGRAMMING or ERASING provides data protection against inadvertent WRITES. In addition, the following hardware data protection measures prevent accidental ERASURE or PROGRAMMING, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC WRITE Inhibit When VCC is less than VLKO, the device does not accept any WRITE cycles. This protects data during VCC power-up and power-down. The system must provide the proper signals to the control pins to prevent unintentional WRITES when VCC is greater than VLKO. Write Pulse “GLITCH” Protection Noise pulses of less than 5ns (typical) on OE\, CSx\ or WEx\ do not initiate a WRITE cycle. Logical Inhibit WRITE cycles are inhibited by holding any one of OE\=VIL, CSx\=VIH or WEx\=VIH. To initiate a WRITE cycle, CSx\ and WEx\ must be a logical zero while OE\ is a logical one. Power-Up WRITE Inhibit If WEx\=CSx\=VIL and OE\=VIH during power-up, the device does not accept commands on the rising edge of WEx\. The internal state machine is automatically reset to READING array data on power-up. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The COMMAND REGISTER TABLE defines the valid register command sequences for this device Module. WRITING incorrect address and data values or WRITING them in the improper sequence resets the device to READING array data. All addresses are latched on the falling edge of WEx\ or CSx\, whichever happens later. All data is latched on the rising edge of WEx\ or CSx\, whichever happens first. Refer to the AC timing references for correct timings of the appropriate signals. Reading Array Data The device is automatically set to READING Array data after device power-up. No commands are required to retrieve data. The device is also ready to READ data after completing an Embedded Program or Embedded Erase operation. After the device accepts an ERASE Suspend command, the device enters the ERASE Suspend Mode. The system can read array data using the standard READ timings, except that if it READS at an address within Erase-Suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend Mode, the system may once again READ array data with the same exception. The system must issue the reset command to re-enable the device for reading array data if DQ5, DQ13, DQ21 and DQ29 goes high, or while in the autoselect mode. NOTES: 1. All protected sectors unprotected 2. All previously protected sectors are protected once again RESET\ = VID (Note 1) Perform Erase or Program Operations RESET\ = VIH Start Temporary Sector Unprotect Completed (Note 2) |
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