© Semiconductor Components Industries, LLC, 2014

September, 2014 − Rev. 11

1

Publication Order Number:

MC74HCT574A/D

MC74HCT574A

Octal 3-State Noninverting

D Flip-Flop with

LSTTL-Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT574A is identical in pinout to the LS574. This

device may be used as a level converter for interfacing TTL or NMOS

outputs to High Speed CMOS inputs.

Data meeting the setup time is clocked to the outputs with the rising

edge of the Clock. The Output Enable input does not affect the states

of the flip−flops, but when Output Enable is high, all device outputs

are forced to the high−impedance state. Thus, data may be stored even

when the outputs are not enabled.

The HCT574A is identical in function to the HCT374A but has the

flip−flop inputs on the opposite side of the package from the outputs to

facilitate PC board layout.

Features

No. 7 A

http://onsemi.com

MARKING DIAGRAMS

SOIC−20

HCT574A

AWLYYWWG

20

1

See detailed ordering and shipping information on page 5 of

this data sheet.

ORDERING INFORMATION

1

20

HCT

574A

ALYW

G

G

TSSOP−20

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G or

G

= Pb−Free Package

(Note: Microdot may be in either location)

SOIC−20

DW SUFFIX

CASE 751D

TSSOP−20

DT SUFFIX

CASE 948E

FUNCTION TABLE

Inputs

Output

OE

Clock

D

Q

LH

H

LL

L

L

L,H,

X

No Change

HX

X

Z

X = don’t care

Z = high impedance

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUT

ENABLE

GND

D7

D6

D5

D3

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

CLOCK

Q7

Q6

Q5

Q4

DATA

INPUTS

D0

219

Q0

D1

D2

D3

D4

D5

D6

D7

CLOCK

OUTPUT ENABLE

3

4

5

6

7

8

9

11

1

18

17

16

15

14

13

12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON-

INVERTING

OUTPUTS

PIN 10 = GND

Figure 1. Logic Diagram