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©2015 Integrated Device Technology, Inc.

Revision C, December 10, 2015

813N252I-09 Datasheet

NOTE 1: Common mode voltage is defined at the cross point.

NOTE 1: Outputs terminated with 50

 to V

AC Electrical Characteristics

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth.

Refer to VCXO-PLL Loop Bandwidth Selection Table.

NOTE 1: Refer to the Phase Noise Plot.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 4: Lock Time measured from power-up to stable output frequency.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input High Current

CLK0, nCLK0,

CLK1, nCLK1

150

µA

Input Low Current

CLK0, CLK1

-10

µA

nCLK0, nCLK1

-150

µA

Peak-to-Peak Input Voltage

0.15

1.3

V

Common Mode Input Voltage; NOTE 1

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Voltage; NOTE 1

V

Output Low Voltage; NOTE 1

V

Peak-to-Peak Output Voltage Swing

0.6

1.0

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Frequency

0.008

155.52

MHz

Output Frequency

25

312.5

MHz

tjit(Ø)

RMS Phase Jitter, (Random),

NOTE 1

Integration Range: 12kHz – 20MHz

0.25

0.35

ps

tjit(pk-pk)

Peak-to-Peak Jitter

1e-12 BER

25

ps

tsk(o)

Output Skew; NOTE 2, 3

25

ps

Output Rise/Fall Time

20% to 80%

140

400

ps

odc

Output Duty Cycle

48

52

%

VCXO & FemtoClock PLL

Lock Time; NOTE 4

6S