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843S1333DGLF Datasheet(PDF) 9 Page - Integrated Device Technology |
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843S1333DGLF Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 15 page 9 ©2015 Integrated Device Technology, Inc Revision A December 2, 2015 843S1333D Data Sheet Schematic Example Figure 5 shows an example of the ICS843S133D application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 20MHz crystal is used. The C1 and C2 = 28pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL termination are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. Figure 5. 843S1333D Schematic Example R4 82.5 Set Logic Input to '0' VCCA C1 28pF + - 1 8 p F VCC C2 28pF C5 0.01u Zo = 50 Ohm OE Zo = 50 Ohm VCC=3.3V R3 133 RU1 1K VCC VCC Set Logic Input to '1' R5 82.5 XTAL_IN Logic Control Input Examples C4 10uF RD2 1K VCC VCC XTAL_OUT Optional Y-Termination + - R6 50 nQ 3.3V Zo = 50 Ohm RD1 Not Install R8 50 R2 133 R7 50 Zo = 50 Ohm C3 0.01u To Logic Input pins X1 20MHz To Logic Input pins R1 10 RU2 Not Install U1 1 2 3 4 8 7 6 5 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ OE Q |
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