W24L01

128K

× 8 CMOS STATIC RAM

Publication Release Date: January 2, 2002

- 1 -

Revision A6

GENERAL DESCRIPTION

The W24L01 is a normal-speed, very low-power CMOS static RAM organized as 131072

× 8 bits that

operates on a wide voltage range from 2.7V to 3.6V power supply. The W24L01 family, W24L01-LE

and W24L01-LI, can meet the requirement of various operating temperature. This device is

manufactured using Winbond's high performance CMOS technology.

FEATURES

one TSOP (8 mm

× 20 mm), small type one

TSOP (8 mm

× 13.4 mm) and 48-pin CSP

PIN CONFIGURATIONS

BLOCK DIAGRAM

48-pin CSP TOP VIEW

1

2

3

4

5

6

A

A0

A1

CS2

A3

A6

A8

B

I/O5

A2

WE

A4

A7

I/O1

C

I/O6

NC

A5

I/O2

D

E

F

I/O7

NC

NC

I/O3

G

I/O8

OE

CS1

A16

A15

I/O4

H

A9

A10

A11

A12

A13

A14

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32-pin

SOP

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

I/O4

I/O5

I/O6

I/O7

I/O8

CS

1

A10

OE

A1

1

A9

A

8

A1

3

WE

CS2

A1

5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A3

A2

A1

A0

OE

A10

CS1

I/O7

I/O6

I/O5

I/O4

32-pin

TSOP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

I/O8

A15

A12

A7

A6

A5

A4

V

CS2

WE

A13

A8

DD

A11

A9

A14

A16

I/O3

I/O2

I/O1

NC

CORE CELL ARRAY

1024 ROWS

128 X 8 COLUMNS

DATA

CNTRL.

CLK

GEN.

R

O

W

D

E

C

O

D

E

R

A15

I/O CKT.

COLUMN DECODER

WE

OE

CLK GEN.

PRECHARGE CKT.

A13 A8 A1A0 A11A10

CS1

CS2

A16

A14

A12

A4

A3

A2

A7

A6

A5

A9

I/O1

I/O8

:

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0

− A16

Address Inputs

I/O1

− I/O8

Data Inputs/Outputs

Chip Select Input

WE

Write Enable Input

OE

Output Enable Input

Power Supply

Ground

NC

No Connection