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BU9409FV Datasheet(PDF) 9 Page - Rohm |
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BU9409FV Datasheet(HTML) 9 Page - Rohm |
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9 / 58 page  Technical Note 9/54 BU9409FV www.rohm.com 2012.03 - Rev.A © 2012 ROHM Co., Ltd. All rights reserved. 1 1--3 3.. C Co on nttrro oll s siig gn na all s sp pe ec ciiffiic ca attiio on n ○ Bus line, I/O stage electrical specification and timing. Fig.1-1: Timing chart Table 1-1: SDAI and SCLI bus-line characteristic (Unless specified, Ta=25 , Vcc=3.3V) Parameter Code High-speed mode Unit Min. Max. 1 SCLI clock frequency fSCL 0 400 kHz 2 Bus-free-time between "Stop" condition and "Start" condition tBUF 1.3 － μs 3 "Start" condition of hold-time (resending). After this period, the first clock-pulse is generated. tHD;STA 0.6 － μs 4 LOW status hold-time of SCLI clock tLOW 1.3 － μs 5 HIGH status hold-time of SCLI clock tHIGH 0.6 － μs 6 Setup time of resending “Start” condition tSU;STA 0.6 － μs 7 Data-hold-time tHD;DAT 0 1) － μs 8 Data-setup time tSU;DAT 500/250/15 0 － ns 9 Rising time of SDAI and SCL signal tR 20+Cb 300 ns 10 Fall time of SDAI and SCL signal tF 20+Cb 300 ns 11 Setup time of "Stop" condition tSU;STO 0.6 － μs 12 Capacitive load of each bus-line Cb － 400 pF The above-mentioned numerical values are all the values corresponding to VIH min and VIL max level. 1) To exceed an undefined area on falling edged of SCLI, transmission device should internally offer the hold-time of 300ns or more for SDAI signal(VIH min of SCLI signal). 2) Data-setup time changes with setup of MCLK. In MCLK=512fs, data setup time is 150ns. In MCLK=256fs, data setup time is 250ns. In MCLK=128fs, data setup time is 500ns. The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection. When problem occurs by any chance, we talk in good faith and correspond. Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V. tBUF tLOW tR tHD;STA S P tHD;DAT tF tHIGH tSU;DAT tSU;STA Sr tHD;STA tSU;STO P SDAI SCLI |
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