MC74LVX373

http://onsemi.com

2

O0

D0

O1

D1

O2

D2

O3

D3

O4

D4

O5

D5

O6

D6

O7

D7

Figure 1. Logic Diagram

nLE

Q

D

nLE

Q

D

nLE

Q

D

nLE

Q

D

nLE

Q

D

nLE

Q

D

nLE

Q

D

nLE

Q

D

LE

OE

3

4

7

8

13

14

17

18

2

5

6

9

12

15

16

19

11

1

INPUTS

OUTPUTS

OE

LE

Dn

On

OPERATING MODE

L

L

H

H

H

L

H

L

Transparent (Latch Disabled); Read Latch

L

L

L

L

h

l

H

L

Latched (Latch Enabled) Read Latch

L

L

X

NC

Hold; Read Latch

H

L

X

Z

Hold; Disabled Outputs

H

H

H

H

H

L

Z

Z

Transparent (Latch Disabled); Disabled Out-

puts

H

H

L

L

h

l

Z

Z

Latched (Latch Enabled); Disabled Outputs

H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low

Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable

High−to−Low Transition; NC = No Change, State Prior to the Latch Enable High−to−Low Transition; X = High

FLOAT Inputs