© Semiconductor Components Industries, LLC, 2014

August, 2014 − Rev. 7

1

Publication Order Number:

MC74HC589A/D

MC74HC589A

8-Bit Serial or

Parallel-Input/Serial-Output

Shift Register with 3-State

Output

High−Performance Silicon−Gate CMOS

The MC74HC589A device consists of an 8−bit storage latch which

feeds parallel data to an 8−bit shift register. Data can also be loaded

3−state output, allowing this device to be used in bus−oriented

systems.

The HC589A directly interfaces with the SPI serial data port on

CMOS MPUs and MCUs.

Features

Standard No. 7 A

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Figure 1. Logic Diagram

SERIAL

DATA

INPUT

14

15

1

2

3

4

5

6

7

12

11

13

10

A

B

C

D

E

F

G

H

LATCH CLOCK

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

OUTPUT ENABLE

PARALLEL

DATA

INPUTS

DATA

LATCH

SHIFT

REGISTER

GND = PIN 8

9

SERIAL

DATA

OUTPUT

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

MARKING DIAGRAMS

SOIC−16

TSSOP−16

1

16

HC589AG

AWLYWW

HC

589A

ALYW

G

G

1

16

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

G or

G = Pb−Free Package

(Note: Microdot may be in either location)

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

LATCH CLOCK

SERIAL SHIFT/

PARALLEL LOAD

A

OUTPUT

ENABLE

SHIFT CLOCK

E

D

C

B

GND

H

G

F