6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. E

11/26/03

IS62C1024L

-35

-70

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WriteCycleTime

35

—

70

—

ns

CE1toWriteEnd

25

—

60

—

ns

CE2toWriteEnd

25

—

60

—

ns

AddressSetupTimetoWriteEnd

25

—

60

—

ns

AddressHoldfromWriteEnd

0

—

0

—

ns

AddressSetupTime

0

—

0

—

ns

WEPulseWidth

25

—

50

—

ns

DataSetuptoWriteEnd

20

—

30

—

ns

DataHoldfromWriteEnd

0

—

0

—

ns

WELOWtoHigh-ZOutput

—

10

—

25

ns

WEHIGHtoLow-ZOutput

3

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

4. Tested with

OE HIGH.

Notes:

1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

3. Address is valid prior to or coincident with

CE1 LOW and CE2 HIGH transitions.

HIGH-Z

DATA VALID

ADDRESS

OE

CE1

CE2

DOUT