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IS62C1024L-35QI Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS62C1024L-35QI Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 11 page 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 IS62C1024L ISSI® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) -35 -70 Symbol Parameter Min. Max. Min. Max. Unit tWC WriteCycleTime 35 — 70 — ns tSCE1 CE1toWriteEnd 25 — 60 — ns tSCE2 CE2toWriteEnd 25 — 60 — ns tAW AddressSetupTimetoWriteEnd 25 — 60 — ns tHA AddressHoldfromWriteEnd 0 — 0 — ns tSA AddressSetupTime 0 — 0 — ns tPWE(4) WEPulseWidth 25 — 50 — ns tSD DataSetuptoWriteEnd 20 — 30 — ns tHD DataHoldfromWriteEnd 0 — 0 — ns tHZWE(2) WELOWtoHigh-ZOutput — 10 — 25 ns tLZWE(2) WEHIGHtoLow-ZOutput 3 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. READ CYCLE NO. 2(1,3) tRC tOHA tAA tDOE tLZOE tACE1/tACE2 tLZCE1/ tLZCE2 tHZOE HIGH-Z DATA VALID tHZCE ADDRESS OE CE1 CE2 DOUT |
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