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MLX71121KLQAAA-000RE Datasheet(PDF) 11 Page - Melexis Microelectronic Systems |
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MLX71121KLQAAA-000RE Datasheet(HTML) 11 Page - Melexis Microelectronic Systems |
11 / 29 page MLX71121 300 to 930MHz FSK/OOK Receiver 39010 71121 Page 11 of 29 Data Sheet Rev. 012 Mar/15 1.15.1 Averaging Detection Mode The simplest configuration is the averaging or RC inte- gration method. Here an on-chip 100k resistor togeth- er with an external slicer capacitor (CSL) are forming an RC low-pass filter. This way the threshold voltage au- tomatically adjusts to the mean or average value of the analog input voltage. To create a stable threshold voltage, the cut-off fre- quency of the low pass has to be lower than the lowest signal frequency. 100k τ CSL AVG RZ AVG R 1.5 τ A long string of zeros or ones, like in NRZ codes, can cause a drift of the threshold. That’s why a Manchester or other DC-free coding scheme works best. The peak detectors are disabled during averaging de- tection mode, and the output pins PDP and PDN are pulled to ground (S4, S6 are closed). Fig. 7: Data path in averaging detection mode 1.15.2 Peak Detection Mode Peak detection mode has a general advantage over averaging detection mode because of the part attack and slow release times. Peak detection should be used for all non-DC-free codes like NRZ. In this configuration the threshold is generated by using the positive and negative peak detectors. The slicer comparator thresh- old is set to the midpoint between the high output and the low output of the data filter by an on-chip resistance divider. Two external capacitors (CP1, CP2) determine the release times for the positive and negative enve- lope. The two on-chip resistors provide a path for the capacitors to discharge. This allows the peak detectors to dynamically follow peak changes of the data filter output voltage. The attack times are very short due to the high peak detector load currents of about 500uA. The decay time constant mainly depends on the longest time period without bit polarity change. This corre- sponds to the maximum number of consecutive bits with the same polarity (NMAX). 100k τ CP1/2 DECAY NRZ MAX DECAY R N τ Fig. 8: Data path in peak detection mode If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disa- bled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output of the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing of CP1 and CP2 during start-up. CSL PKDET+ PKDET _ OA2 data slicer PDP SLC S1 100k S2 S3 S4 Control logic DTAO CINT VCC PDN S5 S6 data filter SLCSEL switches CP1 CP2 PKDET+ PKDET _ OA2 data slicer PDP PDN SLC S1 100k S2 S3 S4 VCC S5 S6 Control logic DTAO CINT data filter SLCSEL switches |
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