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MAX6964AEG Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX6964AEG Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 23 page 17- LED /GPO 4 _______________________________________________________________________________________ PORT OUTPUT LOW VOLTAGE WITH 50mA LOAD CURRENT vs. TEMPERATURE 0.1 0.2 0.3 0.4 0.5 0.6 0 TEMPERATURE ( °C) 110 95 65 80 -10 5 20 35 50 -25 -40 125 V+ = 3.6V V+ = 2.7V V+ = 2V PORT OUTPUT LOW VOLTAGE WITH 20mA LOAD CURRENT vs. TEMPERATURE TEMPERATURE ( °C) 110 95 80 65 50 35 20 5 -10 -25 0.1 0.2 0.3 0.4 0.5 0.6 0 -40 125 ALL OUTPUTS LOADED V+ = 3.6V V+ = 2.7V V+ = 2V PWM CLOCK FREQUENCY vs. TEMPERATURE TEMPERATURE ( °C) 110 95 80 65 50 35 20 5 -10 -25 -40 125 V+ = 3.6V V+ = 2.7V V+ = 2V 0.925 0.950 0.975 1.000 1.025 1.050 0.900 NORMALIZED TO V+ = 3.3V, TA = 25 °C STANDBY CURRENT vs. TEMPERATURE TEMPERATURE ( °C) 110 95 65 80 -10 5 20 35 50 -25 1 2 3 4 5 6 7 8 9 10 0 -40 125 V+ = 3.6V PWM ENABLED V+ = 2.7V PWM ENABLED V+ = 2V PWM DISABLED V+ = 2.7V PWM DISABLED V+ = 3.6V PWM DISABLED V+ = 2V PWM ENABLED SUPPLY CURRENT vs. TEMPERATURE (PWM DISABLED; fSCL = 400kHz) TEMPERATURE ( °C) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 70 0 -40 125 V+ = 3.6V V+ = 2.7V V+ = 2V 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0 SUPPLY CURRENT vs. TEMPERATURE (PWM ENABLED; fSCL = 400kHz) TEMPERATURE ( °C) 110 95 65 80 -10 5 20 3550 -25 -40 125 V+ = 3.6V V+ = 2.7V V+ = 2V ___________________________________________________________________ (TA = +25°C, unless otherwise noted.) TIMING CHARACTERISTICS (continued) (Typical Operating Circuit, V+ = 2V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Capacitive Load for Each Bus Line Cb (Note 3) 400 pF RST Pulse Width tW 1ns Output Data Valid tDV Figure 10 5 ns Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 5: ISINK ≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. |
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