3

Exposed

Thermal Pad

9

10

11

12

8

7

6

5

4

2

1

16

15

14

13

PVIN

PVIN

AVIN

SS/TR

SW

SW

SW

PG

3

TPS62130A-Q1, TPS62133A-Q1, TPS6213013A-Q1

www.ti.com

SLVSCC2B – MAY 2014 – REVISED NOVEMBER 2016

Product Folder Links: TPS62130A-Q1 TPS62133A-Q1 TPS6213013A-Q1

Submit Documentation Feedback

Copyright © 2014–2016, Texas Instruments Incorporated

5 Device Comparison Table

PART NUMBER

OUTPUT VOLTAGE

PACKAGE MARKING

TPS62130A-Q1

adjustable

PA6IQ

TPS62133A-Q1

5 V

PA6JQ

TPS6213013A-Q1

1.3 V

13013Q

(1)

For more information about connecting pins, see Detailed Description and Application and Implementation sections.

(2)

An internal pull-down resistor keeps logic level low, if pin is floating.

(3)

See Figure 46.

6 Pin Configuration and Functions

VQFN Package

16-Pin

Top View

space

Pin Functions

I/O

DESCRIPTION

NO.

NAME

1,2,3

SW

O

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

4

PG

O

up resistor)

5

FB

I

Voltage feedback pin. Connect resistive voltage divider to this pin.

6

AGND

Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

7

LOG

I

This pin is used for internal logic and must be connected to GND.

8

DEF

I

9

SS/TR

I

Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise

time. It can be used for tracking and sequencing.

10

AVIN

I

Supply voltage for control circuitry. Connect to same source as PVIN.

11,12

PVIN

I

Supply voltage for power stage. Connect to same source as AVIN.

13

EN

I

14

VOS

I

Output voltage sense pin and connection for the control loop circuitry.

15,16

PGND

Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

Exposed Thermal Pad

–

achieve appropriate power dissipation and mechanical reliability.