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TPS65132B2YFFR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS65132B2YFFR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 65 page PowerPAD 1 16 7 20 8 19 9 18 10 17 2 15 3 14 4 13 5 12 6 11 PGND OUTP PGND OUTP AGND REG VIN CFLY1 ENP PGND ENN PGND RVC package (bottom view) RVC package (top view) PowerPAD 1 16 7 20 8 19 9 18 10 17 2 15 3 14 4 13 5 12 6 11 PGND OUTP PGND OUTP AGND REG VIN CFLY1 ENP PGND ENN PGND 7 TPS65132 www.ti.com SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016 Product Folder Links: TPS65132 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated QFN Package 20 Pins Pin Functions PIN I/O DESCRIPTION NAME Wx AGND 3 — Analog ground 17 CFLY1 13 I/O Negative charge pump flying capacitor pin CFLY2 10 I/O Negative charge pump flying capacitor pin ENN 6 I Enable pin for VNEG rail ENP 5 I Enable pin for VPOS rail OUTP 16 O Output pin of the LDO (VPOS) 15 OUTN 9 O Output pin of the negative charge pump (VNEG) PGND 1 — Power ground 2 11 12 REG 14 I/O Boost converter output pin 18 SCL 8 I/O I²C interface clock signal pin SDA 7 I/O I²C interface data signal pin SW 19 I/O Switch pin of the boost converter 20 VIN 4 I Input voltage supply pin |
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