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ADS7803BP Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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ADS7803BP Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 13 page 5 ® ADS7803 TYPICAL PERFORMANCE CURVES (CONT) At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, dynamic performance based on 2048 point FFTs , unless otherwise noted. THEORY OF OPERATION ADS7803 uses the advantages of advanced CMOS technol- ogy (logic density, stable capacitors, precision analog switches, and low power consumption) to provide a precise 12-bit analog-to-digital converter with on-chip sampling and four-channel analog-input multiplexer. The input stage consists of an analog multiplexer with an address latch to select from four input channels. The converter stage consists of an advanced successive approximation architecture using charge redistribution on a capacitor network to digitize the input signal. A tempera- ture-stabilized differential auto-zeroing circuit is used to minimize offset errors in the comparator. Linearity errors in the binary weighted main capacitor network are corrected using a capacitor trim network and correction factors stored in on-chip memory. The correction terms are calculated by an on-chip microcontroller during a calibration cycle, initiated either by power-up or by applying an external calibration signal at any time. During conver- sion, the correct trim capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. With all of the capacitors in both the main array and the trim array on the same chip, excellent stability is achieved, both over temperature and over time. For flexibility, timing circuits include both an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and three- state input/output registers simplify interfacing ADS7803 to most micro-controllers, microprocessors or digital storage systems. The on-chip sampling provides excellent dynamic perfor- mance for input signals to 50kHz, and has a full-power –3dB bandwidth of 4MHz. Full control over sample-to-hold timing is available for applications where this is critical. Finally, this performance is matched with the low-power advantages of CMOS structures to allow a typical power consumption of 10mW, with a 50 µW power down option. OPERATION BASIC OPERATION Figure 1 shows the simple circuit required to operate ADS7803 in the Transparent Mode, converting a single input channel. A convert command on pin 20 (WR) starts a conversion. Pin 22 (BUSY) will output a LOW during the conversion process (including sample acquisition and con- version), and rises only after the conversion is completed. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE). FIGURE 1. Basic Operation. SFR AIN0 AIN1 AIN2 AIN3 V REF+ V REF– DGND V D D7 D6 D5 D4 D3 V A AGND CAL A1 A0 CLK BUSY HBE WR CS RD D0 D1 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Read Command Convert Command High Byte Enable Command BUSY 10nF +5V 10µF 100k Ω NC 10µF 10nF + +5V NC Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 BUSY LOW LOW LOW Data Bit 11 (MSB) HBE Input LOW HBE Input HIGH Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 0 (LSB) Data Bit 1 Data Bit 2 HBE Input HIGH HBE Input LOW 0 –5V Input + INTERNAL CLOCK FREQUENCY vs TEMPERATURE Ambient Temperature (°C) –50 100 –25 75 025 50 R CLOCK = 70kΩ 0.9 1.15 1.1 1.05 1 0.95 10 1 INTERNAL CLOCK FREQUENCY vs R CLOCK R CLOCK (kΩ) 0.1 10 1k 100 |
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