SN65MLVD203B datasheet(7/36 Pages) TI1

Part #	SN65MLVD203B

Description	Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protection

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SN65MLVD206B

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SLLSEX9 – DECEMBER 2016

Product Folder Links: SN65MLVD206B

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(1)

All typical values are at 25°C and with a 3.3-V supply voltage.

(2)

Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.

(3)

Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4)

tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.

(5)

Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).

(6)

tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.

6.9 Switching Characteristics – Driver

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

tpLH

Propagation delay time, low-to-high-level output

See Figure 6

2

2.5

3.5

ns

tpHL

Propagation delay time, high-to-low-level output

2

2.5

3.5

ns

tr

Differential output signal rise time

2

ns

tf

Differential output signal fall time

2

ns

tsk(p)

Pulse skew (|tpHL – tpLH|)

30

150

ps

tsk(pp)

Part-to-part skew (2)

0.9

ns

tjit(per)

Period jitter, rms (1 standard deviation)(3)

100-MHz clock input(4)

1

2

ps

tjit(pp)

Peak-to-peak jitter(3)(5)

200 Mbps 215 –1 PRBS input(6)

160

210

ps

tPHZ

Disable time, high-level-to-high-impedance output

See Figure 7

4

7

ns

tPLZ

Disable time, low-level-to-high-impedance output

4

7

ns

tPZH

Enable time, high-impedance-to-high-level output

4

7

ns

tPZL

Enable time, high-impedance-to-low-level output

4

7

ns

(1)

All typical values are at 25°C and with a 3.3-V supply voltage.

(2)

Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.

(3)

Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4)

VID = 200 mVpp (MLVD201B, 203B), VID = 400 mVpp (MLVD206B, 207B), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30K

samples.

(5)

Peak-to-peak jitter includes jitter due to pulse skew (tsk(p))

(6)

VID = 200 mVpp (MLVD201B, 203B), VID = 400 mVpp (MLVD206B, 207B), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100K

samples.

6.10 Switching Characteristics – Receiver

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

CL = 15 pF, See Figure 11

2

6

10

ns

tPHL

Propagation delay time, high-to-low-level output

2

6

10

ns

tr

Output signal rise time

2.3

ns

tf

Output signal fall time

2.3

ns

tsk(p)

Pulse skew (|tpHL – tpLH|)

Type 1

100

300

ps

Type 2

400

750

ps

tsk(pp)

Part-to-part skew(2)

1

ns

tjit(per)

Period jitter, rms (1 standard deviation)(3)

100-MHz clock input(4)

1

ps

tjit(pp)

Peak-to-peak jitter(3) (5)

Type 1

200 Mbps 215 –1 PRBS input(6)

50

650

ps

Type 2

35

650

ps

tPHZ

Disable time, high-level-to-high-impedance output

See Figure 12

6

10

ns

tPLZ

Disable time, low-level-to-high-impedance output

6

10

ns

tPZH

Enable time, high-impedance-to-high-level output

10

15

ns

tPZL

Enable time, high-impedance-to-low-level output

10

15

ns

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