TABLE 2. Pin Descriptions

Pin

Description

Name

No. Pins

I/O

VCC

4

N/A

Power

GND

4

N/A

Ground

D(15:0)

16

I/O

Bidirectional Data Bus. Signals are bonded out for the packaged device. D15 and D14

are shared pins with SCAN_IN, and SCAN_OUT respectively.

D(31:16)

(Note 1)

16

I/O

Bidirectional Data Bus. These signals are not available in the packaged device.

A(4:0)

5

I

Address Bus

SCK

1

I

The system clock that drives all internal timing. TCK_SM is a gated, divided and buffered

version of SCK.

INT

1

O

Interrupt Output

OE

1

I

Output enable that tristates all 1149.1 "_SM" outputs when high.

DTACK

1

O

DTACK is used to synchronize asynchronous transfers between the host and the

STA101. When CE is high, DTACK is tristated. When CE is low, DTACK is enabled.

DTACK goes low when data has been registered and then goes tri-state when the cycle

has completed.

R/W

1

I

R/W defines a PPI cycle. Read when high, write when low.

STB

1

I

Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit mode, are

tristated when STB is high. Data valid setup is with respect to the falling edge of STB

and data valid hold is with respect to rising edge of STB.

CE

1

I

Chip Enable, when low, enables the PPI for data transfers. CE can remain low during

back-to-back accesses. D(15:0), or D(31:0) in 32-bit mode, and DTACK are tristated

when CE is high.

RST

1

I

Asynchronous reset, when low, initializes the STA101.

TDO

1

O

Test Data Out is the serial scan output from the STA101. TDO is enabled when OE is

low.

TDI

1

I

Test Data In is the serial scan input to the STA101.

TMS

1

I

Test Mode Select. The Test Mode Select pin is a serial input used to accept control logic

to the Test & debug interface.

TCK

1

I

Test Clock Input for 1149.1

TRST

1

I

Test Reset. This pin should be tied to ground by a 1K resistor to hold the Test and Debug

Interface in the Test-Logic-Reset state during device power-up. This avoids invalid

states when ramping supply voltages.

TDI_SM

1

I

Scan Master Test Data Input in the Serial Scan Interface

TDO_SM

1

O

Scan Master Test Data Output in the Serial Scan Interface

TMS_SM

1

O

Scan Master Test Mode Select in the Serial Scan Interface

TCK_SM

1

O

Scan Master Test Clock in the Serial Scan Interface

TRST0_SM

1

O

Scan Master Test Reset output in the Serial Scan Interface

TRST1_SM

(Note 1)

1

O

Redundent ScanMaster TRST. This signal is not available for the packaged device.

TRIST_SM

1

O

The TRI-STATE notification pin exerts a high signal when TDO_SM is TRI-STATED

Note 1:

D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged part. These are used in

the 32-bit Macro Mode only.

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