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EM44CM0884LBA-25E Datasheet(PDF) 2 Page - Eorex Corporation |
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EM44CM0884LBA-25E Datasheet(HTML) 2 Page - Eorex Corporation |
2 / 28 page EM44CM0884LBA Dec. 2014 2/28 www.eorex.com 512Mb (16M×4Bank×8) Double DATA RATE 2 SDRAM Features • JEDEC Standard VDD/VDDQ = 1.8V±0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS • Bust length: 4 and 8. • Programmable CAS Latency (CL): 5, 6, 7 • Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 & 6. • Write Latency (WL) =Read Latency (RL) -1. • Read Data Strobe (RDQS) supported • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition with CK transition. • DM mask write data-in at the both rising and falling edges of the data strobe. • Sequential & Interleaved Burst type available. • Off-Chip Driver (OCD) Impedance Adjustment • On Die Termination (ODT) • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms • 7.8us at average periodic refresh interval • RoHS Compliance • tRAS lockout supported • High Temperature Self-Refresh rate enable Description The EM44CM0884LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with high performance CMOS process containing 536,870,912 bits which organized as 16Mbits x 4 banks by 8 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 800 MT/sec (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 512Mb DDR2 devices operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ. Available package: FBGA-60Ball (with 0.8mm x 0.8mm ball pitch) |
Similar Part No. - EM44CM0884LBA-25E |
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Similar Description - EM44CM0884LBA-25E |
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