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72V51233L6BB Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 72V51233L6BB
Description  3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72V51233L6BB Datasheet(HTML) 8 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PAE
Programmable
LVTTL
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
(P10)
Almost-EmptyFlag OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAEn bus lines. This flag is
synchronized to RCLK.
PAEn
Programmable
LVTTL
Onthe4Qdevicethe
PAEnbusis4bitswide.ThisoutputbusprovidesPAEstatusofall4queues,withina
(
PAE3-P13
Almost-Empty
OUTPUT
selected device. During queue read/write operations these outputs provide programmable empty flag
PAE2-R13
Flag Bus
status in either director polled mode. The mode of flag operation is determined during master reset via
PAE1-T13
thestateof theFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansion
PAE0-T14)
of multi-queuedevices.Duringdirectoperationthe
PAEnbusisupdatedtoshowthePAEstatusofqueues
within a selected device. Selection is made using RCLK, ESTR and Flag Bus RDADD. During Polled
operation the
PAEnbusisloadedwiththePAEstatusofmulti-queueflow-controldevicessequentially
based on the rising edge of RCLK.
PAF
Programmable
LVTTL
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
(R8)
Almost-FullFlag
OUTPUT
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
is almost-full. This flag output may be duplicated on one of the
PAFnbuslines.Thisflagissynchronized
toWCLK.
PAFn
Programmable
LVTTL
On the 4Q device the
PAFnbusis4bitswide.ThisoutputbusprovidesPAFstatusofall4queues,withina
(
PAE3-P5
Almost-Full
OUTPUT
selecteddevice.Duringqueueread/writeoperationstheseoutputsprovideprogrammablefullflagstatus,
PAE2-R5
Flag Bus
in either direct or polled mode. The mode of flag operation is determined during master reset via the state
PAE1-T5
of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of
PAE0-T4)
multi-queuedevices.Duringdirectoperationthe
PAFnbusisupdatedtoshowthePAFstatusofaqueues
within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled
operation the
PAFn bus is loaded with thePAF status of multi-queue flow-control devices sequentially
based on the rising edge of WCLK.
PRS
PartialReset
LVTTL
APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
(T8)
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
Q[17:0]
Data Output Bus
LVTTL
These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge
Qout (See Pin
OUTPUT
of RCLK provided that
REN is LOW, OE is LOW and the queue is selected. Due to bus matching not
table for details)
all outputs may be used, any unused outputs should not be connected.
RADEN
Read Address
LVTTL
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
(R14)
Enable
INPUT
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.
Note, that a read queue selection cannot be made, (RADEN must NOT go active) until programming of
the part has been completed and
SENO has gone LOW.
RCLK
Read Clock
LVTTL
When enabled by
REN, the rising edge of RCLK reads data from the selected queue via the output bus
(T10)
INPUT
Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while
RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the device
to be placed on the
PAEn bus during direct flag operation. During polled flag operation the PAEn bus is
cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The
PAE and OVoutputs
are all synchronized to RCLK. During device expansion the EXO and EXI signals are based on RCLK.
RCLK must be continuous and free-running.
RDADD
Read Address Bus
LVTTL
For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
[5:0]
INPUT
functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant2bitsofthebus,RDADD[1:0]
(See next page
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Addresspin,RDADD[2]provides
fordetails)
the user with a Null-Q address. If the user does not wish to address one of the 4 queues, a Null-Q can
be addressed using this pin. The Null-Q operation is discussed in more detail later. The most significant
3 bits, RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
I/O TYPE
Description
Pin No.


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