Electronic Components Datasheet Search |
|
72V51253L6BBI Datasheet(PDF) 6 Page - Integrated Device Technology |
|
72V51253L6BBI Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 50 page 6 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits D[17:0] Data Input Bus LVTTL These are the 18 data input pins. Data is written into the device via these input pins on the rising edge Din (See Pin INPUT of WCLK provided that WENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs table for details) should be tied LOW. DF(1) Default Flag LVTTL If the user requires default programming of the multi-queue device, this pin must be setup before Master (L3) INPUT Reset and must not toggle during any device operation. The state of this input at master reset determines the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128. DFM(1) Default Mode LVTTL The multi-queue device requires programming after master reset. The user can do this serially via the (L2) INPUT serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be selected, if HIGH then default mode is selected. ESTR PAEn Flag Bus LVTTL If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK (R15) Strobe INPUT and the RDADD bus to select a device for its queues to be placed on to the PAEn bus outputs. A device addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted and SENO has gone LOW. ESYNC PAEn Bus Sync LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus (R16) OUTPUT during Polled operation of the PAEn bus. During Polled operation each devices queue status flags are loadedontothe PAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1 onto PAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected device is placed on to the PAEn bus, the ESYNC output will be HIGH. EXI PAEnBus LVTTL The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn/ (T16) Expansion In INPUT bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied LOW if the PAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput must be connected to the EXO output of the same device. In expansion mode the EXI of the first device should be tied LOW, when direct mode is selected. EXO PAEnBus LVTTL EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled (T15) Expansion Out OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This pinpulsesHIGHwhendeviceNplacesits PAEstatusontothePAEnbuswithrespecttoRCLK.Thispulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising edge the first quadrant of device N+1 will be loaded on to the PAEn bus. This continues through the chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device in the chain provides synchronization to the user of this looping event. FF Full Flag LVTTL This pin provides the full flag output for the active queue, that is, the queue selected on the input port (P8) OUTPUT for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue on the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during expansionofdevices,whenthe FFflagoutputofupto8devicesmaybeconnectedtogetheronacommon line. The device with a queue selected takes control of the FF bus,allotherdevicesplacetheirFFoutput into High-Impedance. When a queue selection is made on the write port this output will switch from High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK. FM(1) Flag Mode LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the (K16) INPUT FMpinduringMasterResetwilldeterminewhetherthe PAFnandPAEnflagbussesoperateineitherPolled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct. FSTR PAFn Flag Bus LVTTL If direct operation of the PAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK (R4) Strobe INPUT and the WRADD bus to select a device for its queues to be placed on to the PAFn bus outputs. A device addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted and SENO has gone LOW. PIN DESCRIPTIONS Symbol & Name I/O TYPE Description Pin No. |
Similar Part No. - 72V51253L6BBI |
|
Similar Description - 72V51253L6BBI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |