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72V82L20PAG8 Datasheet(PDF) 6 Page - Integrated Device Technology |
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72V82L20PAG8 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 12 page  6 COMMERCIAL ANDINDUSTRIAL TEMPERATURERANGES IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Figure 5. Empty Flag From Last Read to First Write Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse Figure 6. Retransmit FF R W tRFF tWPF 3966 drw 10 EF W R tWEF tRPE 3966 drw 09 tRTC tRT tRTS RT W,R HF, EF, FF tRTR FLAG VALID tRTF 3966 drw 08 LAST READ R IGNORED READ FIRST WRITE ADDITIONAL WRITES W EF tWEF VALID tA DATA OUT tREF 3966 drw 07 FIRST READ VALID |
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