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K7N321801M-QC25 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K7N321801M-QC25 Datasheet(HTML) 5 Page - Samsung semiconductor |
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5 / 24 page  1Mx36 & 2Mx18 Pipelined NtRAMTM - 5 - Rev 2.0 Nov. 2003 K7N321801M K7N323601M PIN CONFIGURATION(TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin TQFP (20mm x 14mm) N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. K7N321801M(2Mx18) PIN NAME NOTE : A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. A 0 - A 20 ADV WE CLK CKE CS1 CS2 CS2 BW x(x=a,b) OE ZZ LBO Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control 32,33,34,35,36,37,43 44,45,46,47,48,49,50, 80,81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 VDD VSS N.C. DQa0~a 8 DQb0~b 8 VDDQ VSSQ Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Output Power Supply (3.3V or 2.5V) Output Ground 14,15,16,41,65,66,91 17,40,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,51,52,53, 56,57,75,78,79,95,96 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 |
Similar Part No. - K7N321801M-QC25 |
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Similar Description - K7N321801M-QC25 |
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