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K7N803601B-QC13 Datasheet(PDF) 3 Page - Samsung semiconductor |
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K7N803601B-QC13 Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 18 page 256Kx36 & 512Kx18 Pipelined NtRAMTM - 3 - Rev 3.0 Nov. 2003 K7N803601B K7N801801B 256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM The K7N803601B and K7N801801B are 9,437,184 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory uti- lizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N803601B and K7N801801B are implemented with SAMSUNG ′s high performance CMOS technology and is avail- able in 100pin TQFP and Multiple power and ground pins mini- mize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • Α interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • 100-TQFP-1420A • Operating in commercial and industrial temperature range. FAST ACCESS TIMES PARAMETER Symbol -16 -13 Unit Cycle Time tCYC 6.0 7.5 ns Clock Access Time tCD 3.5 4.2 ns Output Enable Access Time tOE 3.5 3.8 ns WE BWx CLK CKE CS1 CS2 CS2 ADV OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 ADDRESS ADDRESS REGISTER A ′0~A′1 36 or 18 DQPa ~ DQPd OUTPUT BUFFER REGISTER DATA-IN REGISTER DATA-IN REGISTER K K K REGISTER BURST ADDRESS COUNTER WRITE ADDRESS REGISTER WRITE CONTROL LOGIC K A [0:17] or LBO A2~A17 or A2~A18 A0~A1 (x=a,b,c,d or a,b) 256Kx36 , 512Kx18 MEMORY ARRAY NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba. A [0:18] |
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