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DSP56374 Datasheet(PDF) 2 Page - Motorola, Inc |
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DSP56374 Datasheet(HTML) 2 Page - Motorola, Inc |
2 / 128 page 2 PRELIMINARY Freescale Semiconductor Features Figure 1. DSP56374 Block Diagram 1Features 1.1 DSP56300 Modular Chassis • 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V. • Object Code Compatible with the 56K core. • Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support. • Program Control with position independent code support. • Six-channel DMA controller. • Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise • Internal address tracing support and OnCE for Hardware/Software debugging. • JTAG port, supporting boundary scan, compliant to IEEE 1149.1. • Very low-power CMOS design, fully static design with operating frequencies down to DC. • STOP and WAIT low-power standby modes. PLL OnCE Clock Gen. YAB XAB PAB YDB XDB PDB GDB MODB/IRQB/GPIO MODC/IRQC/GPIO DSP56300 12 24-Bit DDB DAB Peripheral Core Expansion Area JTAG 4 5 RESET MODA/IRQA/GPIO PINIT/NMI EXTAL Address Generation Unit Six Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24+56→56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Mgmt. Memory Expansion Area X Data RAM 6k × 24 Y Data RAM 6k × 24 Bootstrap ROM Internal Data Bus Switch SHI GPIO ESAI ESAI_1 Interface Interface Interface 12* 15* Triple 3 ROM 4k × 24 ROM 4k × 24 Program RAM 6k × 24 ROM 20k × 24 XTAL MODD/IRQD/GPIO Timer Watch dog Timer * ESAI_1 and dedicated GPIO pins are not available in the 52-pin package. |
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