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THS4552IRTWT Datasheet(PDF) 6 Page - Texas Instruments |
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THS4552IRTWT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 71 page  6 THS4552 SBOS831 – DECEMBER 2016 www.ti.com Product Folder Links: THS4552 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. (2) This slew rate is the average of the rising and falling time estimated from the sinusoidal large-signal bandwidth as: (VP / √2) × 2π × f–3dB. (3) Currents out of pin are treated as a positive polarity (with the exception of the power-supply pins). (4) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); specifications are per channel; see Figure 61 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) AC PERFORMANCE SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB) 150 MHz C VOUT = 20 mVPP, G = 2 75 C VOUT = 20 mVPP, G = 10 15 C GBP Gain-bandwidth product VOUT = 20 mVPP, G = 100 135 MHz C LSBW Large-signal bandwidth VOUT = 2 VPP, G = 1 37 MHz C Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 1 15 MHz C SR Slew rate(2) VOUT = 4 VPP, full-power bandwidth (FPBW), RL = 1 kΩ 220 V/µs C tR, tF Rise and fall time VOUT = 0.5-V step, G = 1, input tR = 2 ns 6 ns C tSETTLE Settling time To 0.1%, VOUT = 0.5-V step, input tR = 2 ns, G = 1 30 ns C To 0.01%,VOUT = 0.5-V step, input tR = 2 ns, G = 1 50 C Overshoot and undershoot VOUT = 0.5-V step G = 1, input tR = 2 ns 8% C HD2 Second-order harmonic distortion f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –128 dBc C f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ –124 C HD3 Third-order harmonic distortion f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –139 dBc C f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ –131 C Input voltage noise f > 500 Hz, 1/f < 150 Hz 3.3 nV/ √Hz C Input current noise f > 20 kHz, 1/f <10 kHz 0.5 pA/ √Hz C Overdrive recovery time G = 2, 2X output overdrive, dc coupled 50 ns C Closed-loop output impedance f = 100 kHz (differential), G = 1 0.02 Ω C Channel-to-channel crosstalk 2-VPP output on one channel, 1 MHz –80 dBc C DC PERFORMANCE(3) AOL Open-loop voltage gain ±3-V differential-to-differential, 1-kΩ load 105 125 dB A VIO Input-referred offset voltage TA = 25°C –175 ±50 175 µV A TA = 0°C to +70°C –225 265 B TA = –40°C to +85°C –295 295 B TA = –40°C to +125°C –295 375 B Input offset voltage drift(4) TA = –40°C to +125°C (PW package) –2.0 ±0.45 2.0 µV/°C B Channel-to-channel input offset voltage mismatch TA = 25°C (PW package) –250 250 µV A Input offset voltage drift mismatch TA = –40°C to +125°C (PW package) –2.7 2.7 µV/°C B IIB Input bias current (positive current out-of-node) TA = 25°C 0.35 1.0 1.5 µA A TA = 0°C to +70°C 0.42 1.73 B TA = –40°C to +85°C 0.22 1.80 B TA = –40°C to +125°C 0.22 2.0 B Input bias current drift(4) TA = –40°C to +125°C 2 3.3 5.0 nA/°C B |
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