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MCP37220-200 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP37220-200 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 116 page  2015-2016 Microchip Technology Inc. DS20005395B-page 3 MCP37210-200 AND MCP37D10-200 Description The MCP37210-200 is a single-channel 200 Msps 12-bit pipelined ADC, with built-in high-order digital decimation filters, Noise-Shaping Requantizer (NSR), gain and offset adjustment. The MCP37D10-200 is also a single-channel 200 Msps 12-bit pipelined ADC, with built-in digital down-conversion in addition to the features offered by the MCP37210-200. Both devices feature harmonic distortion correction and DAC noise cancellation that enables high- performance specifications with SNR of 67 dBFS (typical) and SFDR of 96 dBc (typical). The output decimation filter option improves SNR performance up to 73.5 dBFS with the 64x decimation setting. The NSR feature reshapes the quantization noise level so that most of the noise power is pushed outside the frequency band of interest. As a result, SNR is improved within a selected frequency band of interest, while SFDR is not affected. The digital down-conversion option in the MCP37D10-200 can be utilized with the decimation and quadrature output (I and Q data) options, and offers great flexibility in various digital communication system designs, including cellular base-stations and narrow-band communication systems. These A/D converters exhibit industry-leading low-power performance with only 338 mW operation, while using the LVDS output interface at 200 Msps. This superior low-power operation, coupled with high dynamic performance, makes these devices ideal for portable high-frequency instrumentation, sonar, radar, and high-speed data acquisition systems. These devices also include various features designed to maximize flexibility in the user’s applications and minimize system cost, such as a programmable PLL clock, output data rate control and phase alignment, and programmable digital pattern generation. The device’s operational modes and feature sets are configured by setting up the user-programmable internal registers. The device samples the analog input on the rising edge of the clock. The digital output code is available after 23 clock cycles of data latency. Latency will increase if any of the digital signal post-processing (DSPP) options are enabled. The differential full-scale analog input range is programmable up to 1.8 VP-P. The ADC output data can be coded in two's complement or offset binary representation, with or without the data randomizer option. The output data is available with a full-rate CMOS or Double-Data-Rate (DDR) LVDS interface. The device is available in Pb-free VTLA-124 and TFBGA-121 packages. The device operates over the commercial temperature range of -40°C to +85°C. Package Types (a) VTLA-124 Package. (b) TFBGA-121 Package. Bottom View Dimension: 9 mm x 9 mm x 0.9 mm Bottom View Dimension: 8 mm x 8 mm x 1.08 mm Ball Pitch: 0.65 mm Ball Diameter: 0.4 mm |
Similar Part No. - MCP37220-200 |
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Similar Description - MCP37220-200 |
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