MC74HC112_13 datasheet(4/7 Pages) ONSEMI

Part #	MC74HC112

Description	Dual J-K Flip-Flop with Set and Reset

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MC74HC112A

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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

– 55 to

25_C

v 85_C

v 125_C

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

30

35

4.8

24

28

4.0

20

24

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

4.5

6.0

125

25

21

155

31

26

190

38

32

ns

tPLH,

tPHL

Maximum Propagation Delay, Reset to Q or Q

(Figures 2 and 4)

2.0

4.5

6.0

155

31

26

195

39

33

235

47

40

ns

tPLH,

tPHL

Maximum Propagation Delay, Set to Q or Q

(Figures 2 and 4)

2.0

4.5

6.0

165

33

28

205

41

35

250

50

43

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

Cin

Maximum Input Capacitance

—

10

pF

CPD

Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25°C, VCC = 5.0 V

pF

35

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

– 55 to

25_C

v 85_C

v 125_C

tsu

Minimum Setup Time, J or K to Clock

(Figure 3)

2 0

4.5

6.0

100

20

17

125

25

21

150

30

26

ns

th

Minimum Hold Time, Clock to J or K

(Figure 3)

2.0

4.5

6.0

3

ns

trec

Minimum Recovery Time, Set or Reset Inactive to Clock

(Figure 2)

2.0

4.5

6.0

100

20

17

125

25

21

150

30

26

ns

tw

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

80

16

14

100

20

17

120

24

20

ns

tw

Minimum Pulse Width, Set or Reset

(Figure 2)

2.0

4.5

6.0

80

16

14

100

20

17

120

24

20

ns

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

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