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MC74HC112ADG Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC74HC112ADG
Description  Dual J-K Flip-Flop with Set and Reset
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC112ADG Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 8
1
Publication Order Number:
MC74HC112/D
MC74HC112A
Dual J-K Flip-Flop with
Set and Reset
High−Performance Silicon−Gate CMOS
The MC74HC112A is identical in pinout to the LS112. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has active−low
asynchronous Set and Reset inputs.
The HC112A is identical in function to the HC76, but has a different
pinout.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Similar in Function to the LS112 Except When Set and Reset are
Low Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
These are Pb−Free Devices
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
1
16
HC112AG
AWLYWW
HC
112A
ALYWG
G
1
16
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION


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