Electronic Components Datasheet Search |
|
72V3624L15PFG8 Datasheet(PDF) 11 Page - Integrated Device Technology |
|
72V3624L15PFG8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 34 page 11 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 1,024 x 36 x 2 SPM FS1/SEN FS0/SD MRS1 MRS2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) HH H ↑ X64 X HH H ↑↑ 64 64 HH L ↑ X16 X HH L ↑↑ 16 16 HL H ↑ X8 X HL H ↑↑ 88 HL L ↑↑ Parallel programming via Port A Parallel programming via Port A LH L ↑↑ Serial programming via SD Serial programming via SD LH H ↑↑ Reserved Reserved LL H ↑↑ Reserved Reserved LL L ↑↑ Reserved Reserved labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard and FWFT modes. — PRESET VALUES ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM) andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH transition of its Master Reset input (MRS1, MRS2). For example, to load the preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when FlFO1reset(MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2 are loaded with one of the preset values in the same way with FIFO2 Master Reset(MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For relevant preset value loading timing diagram, see Figure 3. — PARALLEL LOAD FROM PORT A ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the first four writes to FIFO1 do not store data in the RAM but load theoffsetregistersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedby the offset registers are (A7-A0) or (A9-A0) for the IDT72V3624 or IDT72V3644, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid program- ming values for the registers range from 1 to 252 for the IDT72V3624; and 1 to 1,020 for the IDT72V3644. After all the offset registers are programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing diagram illustration of parallel programming of the flag offset values. — SERIAL LOAD To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. There are 32- or 40-bit writes needed to complete the programming for the IDT72V3624 or IDT72V3644, respectively. The four registers are written in the order Y1, X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 252 (IDT72V3624) or 1 to 1,020 (IDT72V3644). When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written. FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/IRB) flag also remains LOW throughout the serial programming process, until all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure 6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes) timing diagram. FIFO WRITE/READ OPERATION ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect (CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh- impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA isHIGH,MBAisLOW,and EFA/ORAisHIGH(seeTable2).FIFOreadsand writes on Port A are independent of any concurrent Port B operation. NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. TABLE 1 — FLAG PROGRAMMING |
Similar Part No. - 72V3624L15PFG8 |
|
Similar Description - 72V3624L15PFG8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |