2

COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641

3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36

TQFP (PNG120, order code: PF)

TOP VIEW

NOTE:

1. NC – No internal connection.

DESCRIPTION (CONTINUED)

PIN CONFIGURATION

GND

GND

GND

GND

GND

GND

GND

4658 drw 03

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

Communication between each port may take place with two 36-bit mailbox

registers. Eachmailboxregisterhasaflagtosignalwhennewmailhasbeen

stored. Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.

Expansion is also possible in word depth.

These devices are a clocked FIFO, which means each port employs a

synchronousinterface. AlldatatransfersthroughaportaregatedtotheLOW-

to-HIGHtransitionofacontinuous(free-running)portclockbyenablesignals.

Thecontinuousclocksforeachportareindependentofoneanotherandcan

be asynchronous or coincident. The enables for each port are arranged to

provide a simple interface between microprocessors and/or buses with

synchronouscontrol.

TheInputReady(IR)flagandAlmost-Full(AF)flagoftheFIFOaretwo-stage

synchronizedtoCLKA. TheOutputReady(OR)flagandAlmost-Empty(AE)

flag of the FIFO are two-stage synchronized to CLKB. Offset values for the

Almost-FullandAlmost-EmptyflagsoftheFIFOcanbeprogrammedfromport

A or through a serial input.

The IDT72V3631/72V3641 are characterized for operation from 0

°C to

70

°C. These devices are fabricated using high speed, submicron CMOS

technology.