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72V825L15PFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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72V825L15PFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 26 page  3.3 VOLT CMOS DUAL SyncFIFO™ DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 IDT72V805 IDT72V815 IDT72V825 IDT72V835 IDT72V845 1 NOVEMBER 2016 DSC-4295/6 © 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER OFFSET REGISTER FLAG LOGIC FFA/IRA PAFA EFA/ ORA PAEA HFA/(WXOA) READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER EXPANSION LOGIC RESET LOGIC WENA DA0-DA17 LDA RSA ( HFA)/WXOA WXIA RENA RCLKA OEA QA0-QA17 RXOA RXIA FLA WCLKA INPUT REGISTER OUTPUT REGISTER RAM ARRAY 256 x 18 512 x 18 1,024 x 18 2,048 x 18 4,096 x 18 OFFSET REGISTER FLAG LOGIC FFB/IRB PAFB EFB/ORB PAEB HFB/(WXOB) READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER EXPANSION LOGIC RESET LOGIC WENB DB0-DB17 LDB RSB ( HFB)/WXOB WXIB RENB RCLKB OEB QB0-QB17 RXOB RXIB FLB WCLKB 4295 drw 01 RAM ARRAY 256 x 18 512 x 18 1,024 x 18 2,048 x 18 4,096 x 18 FEATURES: ••••• The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs ••••• The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs ••••• The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs ••••• The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs ••••• The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs ••••• Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint ••••• Ideal for the following applications: – Network switching – Two level prioritization of parallel data – Bidirectional data transfer – Bus-matching between 18-bit and 36-bit data paths – Width expansion to 36-bit per package – Depth expansion to 8,192 words per package ••••• 10 ns read/write cycle time ••••• 5V input tolerant ••••• IDT Standard or First Word Fall Through timing ••••• Single or double register-buffered Empty and Full Flags ••••• Easily expandable in depth and width ••••• Asynchronous or coincident Read and Write Clocks ••••• Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings ••••• Half-Full flag capability ••••• Output enable puts output data bus in high-impedance state ••••• High-performance submicron CMOS technology ••••• Available in a 128-pin thin quad flatpack (TQFP) ••••• Industrial temperature range (–40°C to +85°C) is available ••••• Green parts available, see ordering information DESCRIPTION: The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories designed to run off a 3.3V supply for exceptionally low power consumption. One dual IDT72V805/72V815/72V825/72V835/72V845deviceisfunctionallyequiva- lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, |
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