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72V3643L15PFG8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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72V3643L15PFG8 Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 28 page  11 COMMERCIAL TEMPERATURERANGE IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING 256 x 36, 1,024 x 36 TABLE 1 — FLAG PROGRAMMING SPM FS1/SEN FS0/SD RS1 X AND Y REGlSTERS(1) HH H ↑ 64 HH L ↑ 16 HL H ↑ 8 HL L ↑ Parallel programming via Port A LH L ↑ Serial Programming via SD LH H ↑ reserved LL H ↑ reserved LL L ↑ reserved NOTE: 1. X register holds the offset for AE; Y register holds the offset for AF. — PARALLEL LOAD FROM PORT A To program the X and Y registers from Port A, perform a Reset on with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of RS1. After this reset is complete, the first two writes to the FIFO do not store data in RAM. The first two write cycles load the offset registers in the order Y, X. On the third write cycle the FIFO is ready to be loaded with a data word. See Figure 5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT modes), for a detailed timing diagram. The Port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3623 or IDT72V3643, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252 for the IDT72V3623; and 1 to 1,020 for the IDT72V3643. After all the offset registers are programmed from Port A, the FIFO begins normal opera- tion. — SERIAL LOAD ToprogramtheXandYregistersserially,initiateaResetwithSPMLOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of RS1 . After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. There are 16-, 18- or 20-bit writes needed to complete the programming for the IDT72V3623 or the IDT72V3643, respectively. The two registers are written in the order Y, X. Each register value can be programmed from 1 to 252 (IDT72V3623) or 1 to 1,020 (IDT72V3643). Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/ Input Ready (FF/IR) flag remains LOW until all register bits are written. FF /IR is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation. See Figure 6, Serial Programming of the Almost-Full Flag and Almost- Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes). FIFO WRITE/READ OPERATION The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA are LOW. DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see Table 2). FIFO writes on Port A are independent of any concurrent reads on Port B. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are independent of any concurrent writes on Port A. The setup and hold time constraints to the port clocks for the port Chip SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. When operating the FIFO in FWFT mode and the Output Ready flag is LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterby the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH. When the Output Ready flag is HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is clockedtotheoutputregisteronlywhenareadisselectedusingtheport’sChip Select, Write/Read select, Enable, and Mailbox select. Port A Write timing diagram can be found in Figure 7. Relevant Port B Read timing diagrams togetherwithBus-MatchingandEndianselectcanbefoundinFigure8,9and 10. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip- flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asyn- chronously to one another. FF/IR, and AF are synchronized to CLKA. EF/ OR and AE are synchronized to CLKB. Table 4 shows the relationship of each port flag to the number of words stored in memory. |
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