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72V3672L15PQFG Datasheet(PDF) 9 Page - Integrated Device Technology |
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72V3672L15PQFG Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 29 page 9 COMMERCIALTEMPERATURERANGE IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 FEBRUARY 4, 2009 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF IDT72V3652L10(1) IDT72V3652L15 IDT72V3662L10(1) IDT72V3662L15 IDT72V3672L10(1) IDT72V3672L15 Symbol Parameter Min. Max. Min. Max. Unit tA Access Time, CLKA ↑ toA0-A35andCLKB↑ toB0-B35 2 6.5 2 10 ns tPIR Propagation Delay Time, CLKA ↑ to FFA/IRA and CLKB↑ to 2 6.5 2 8 ns FFB/IRB tPOR Propagation Delay Time, CLKA ↑ to EFA/ORA and CLKB↑ to 1 6.5 1 8 ns EFB/ORB tPAE Propagation Delay Time, CLKA ↑ to AEA and CLKB↑ to AEB 1 6.5 1 8 ns tPAF Propagation Delay Time, CLKA ↑ to AFA and CLKB↑ to AFB 1 6.5 1 8 ns tPMF Propagation Delay Time, CLKA ↑ to MBF1 LOW or 0 6.5 0 8 ns MBF2 HIGH and CLKB ↑ to MBF2 LOW or MBF1 HIGH tPMR Propagation Delay Time, CLKA ↑ to B0-B35(2) and 2 8 2 10 ns CLKB ↑toA0-A35(3) tMDV Propagation Delay Time, MBA to A0-A35 valid and 2 6.5 2 10 ns MBB to B0-B35 Valid tPRF Propagation Delay Time, RST1 LOW to AEB LOW, AFA 110 1 15 ns HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH tEN Enable Time, CSA and W/RA LOW to A0-A35 Active 2 6 2 10 ns and CSB LOW and W/RB HIGH to B0-B35 Active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance 1 6 1 8 ns and CSB HIGH or W/RB LOW to B0-B35 at high-impedance NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°. 2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0 °C to +70°C; JEDEC JESD8-A compliant) |
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