IDT72V2103_14 datasheet(9/46 Pages) IDT

Part #	IDT72V2103

Description	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO

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Manufacturer	IDT [Integrated Device Technology]

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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO

8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO

131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 3.3V ± 0.15V, TA = 0

°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for the 7-5ns and 10ns are available as a standard device. All other speed grades are available by special order.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.

Commercial

Com’l & Ind’l(2)

Commercial

BGA & TQFP

TQFP Only

IDT72V2103L6

IDT72V2103L7-5

IDT72V2103L10

IDT72V2103L15

IDT72V2113L6

IDT72V2113L7-5

IDT72V2113L10

IDT72V2113L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

166

—

133.3

—

100

—

66.7

MHz

tA

DataAccessTime(5)

14

1(5)

51(5)

6.5

1(5)

10

ns

tCLK

Clock Cycle Time

6

—

7.5

—

10

—

15

—

ns

tCLKH

Clock High Time

2.7

—

3.5

—

4.5

—

6

—

ns

tCLKL

Clock Low Time

2.7

—

3.5

—

4.5

—

6

—

ns

tDS

DataSetupTime

2

—

2.5

—

3.5

—

4

—

ns

tDH

DataHoldTime

0.5

—

0.5

—

0.5

—

1

—

ns

tENS

EnableSetupTime

2

—

2.5

—

3.5

—

4

—

ns

tENH

EnableHoldTime

0.5

—

0.5

—

0.5

—

1

—

ns

tLDS

LoadSetupTime

3

—

3.5

—

3.5

—

4

—

ns

tLDH

LoadHoldTime

0.5

—

0.5

—

0.5

—

1

—

ns

tRS

ResetPulseWidth(3)

10

—

10

—

10

—

15

—

ns

tRSS

ResetSetupTime

15

—

15

—

15

—

15

—

ns

tRSR

Reset Recovery Time

10

—

10

—

10

—

15

—

ns

tRSF

ResettoFlagandOutputTime

—

15

—

15

—

15

—

15

ns

tRTS

RetransmitSetupTime

3

—

3.5

—

3.5

—

4

—

ns

tOLZ

Output Enable to Output in Low Z(4)

0—

0

—

0—

ns

tOE

OutputEnabletoOutputValid(5)

14

1(5)

61(5)

8ns

tOHZ

Output Enable to Output in High Z(4,5)

14

1(5)

61(5)

8ns

tWFF

Write Clock to FF or IR

—4

—5

—6.5

—

10

ns

tREF

Read Clock to EF or OR

—4

—5

—6.5

—

10

ns

tPAFA

ClocktoAsynchronousProgrammableAlmost-FullFlag

—

10

—

12.5

—

16

—

20

ns

tPAFS

WriteClocktoSynchronousProgrammableAlmost-FullFlag

—

4

—

5

—

6.5

—

10

ns

tPAEA

Clock to Asynchronous Programmable Almost-Empty Flag

—

10

—

12.5

—

16

—

20

ns

tPAES

Read Clock to Synchronous Programmable Almost-Empty Flag

—

4

—

5

—

6.5

—

10

ns

tHF

Clock to HF

—

10

—

12.5

—

16

—

20

ns

tSKEW1

Skew time between RCLK and WCLK for EF/OR and FF/IR

4—

5—

7

—

9—

ns

tSKEW2

Skew time between RCLK and WCLK for PAE and PAF

5—

7—

10

—

14

—

ns

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