Electronic Components Datasheet Search |
|
72V281L15TFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
72V281L15TFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 26 page 3.3 VOLT CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9 IDT72V281 IDT72V291 1 OCTOBER 2014 ©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DSC-4513/4 FEATURES: ••••• Choose among the following memory organizations: IDT72V281 65,536 x 9 IDT72V291 131,072 x 9 ••••• Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs ••••• 10ns read/write cycle time (6.5ns access time) ••••• Fixed, low first word data latency time ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Retransmit operation with fixed, low first word data latency time ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets ••••• Program partial flags by either serial or parallel means ••••• Select IDT Standard timing (using EF EF EF EF EF and FF FF FF FF FF flags) or First Word Fall Through timing (using OR OR OR OR OR and IR IR IR IR IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• Independent Read and Write clocks (permit reading and writing simultaneously) ••••• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin Slim Thin Quad Flat Pack (STQFP) ••••• High-performance submicron CMOS technology ••••• Industrial Temperature Range (-40°C to + 85°C) is available ••••• Green parts available, see ordering information DESCRIPTION: The IDT72V281/72V291 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs,includingthefollowing: ••••• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. ••••• The period required by the retransmit operation is now fixed and short. ••••• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable clock cycle counting delay associated with the latency period found on previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.) FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 65,536 x 9 131,072 x 9 FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0-D8 LD MRS REN RCLK OE Q0-Q8 OFFSET REGISTER PRS FWFT/SI SEN RT 4513 drw 01 |
Similar Part No. - 72V281L15TFGI8 |
|
Similar Description - 72V281L15TFGI8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |