3.3 VOLT CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

IDT72V281

IDT72V291

1

OCTOBER 2014

©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4513/4

FEATURES:

IDT72V281

65,536 x 9

IDT72V291

131,072 x 9

settings

latency time

default to one of two preselected offsets

EF

EF

EF

EF and FF

FF

FF

FF

FF flags) or First Word

Fall Through timing (using OR

OR

OR

OR

OR and IR

IR

IR

IR

IR flags)

simultaneously)

Slim Thin Quad Flat Pack (STQFP)

DESCRIPTION:

The IDT72V281/72V291 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs,includingthefollowing:

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

65,536 x 9

131,072 x 9

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

LD

MRS

REN

RCLK

OE

OFFSET REGISTER

PRS

FWFT/SI

SEN

RT

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