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72V2103L10PFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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72V2103L10PFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 46 page 1 AUGUST 2014 DSC-6119/16 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO 131,072 x 18/262,144 x 9 262,144 x 18/524,288 x 9 IDT72V2103 IDT72V2113 © IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES INPUT REGISTER OUTPUT REGISTER FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN D0 -Dn (x9 or x18) LD MRS REN OE Q0 -Qn (x9 or x18) OFFSET REGISTER PRS FWFT/SI SEN 6119 drw01 BUS CONFIGURATION IW CONTROL LOGIC BE OW IP PFM FSEL0 FSEL1 WCLK/WR RCLK/RD RT RM ASYR ASYW JTAG CONTROL (BOUNDARY SCAN) TCK TMS TDO TDI TRST * * * * * * * * * * RAM ARRAY 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 FEATURES: • Choose among the following memory organizations: IDT72V2103 ⎯ ⎯ ⎯ ⎯ ⎯ 131,072 x 18/262,144 x 9 IDT72V2113 ⎯ 262,144 x 18/524,288 x 9 ••••• Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs ••••• Up to 166 MHz Operation of the Clocks ••••• User selectable Asynchronous read and/or write ports (BGA Only) ••••• 6 ns read/write cycle time (4.0 ns access time) ••••• User selectable input and output port bus-sizing - x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out ••••• Big-Endian/Little-Endian user selectable byte representation ••••• 5V tolerant inputs ••••• Fixed, low first word latency ••••• Zero latency retransmit ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets ••••• Selectable synchronous/asynchronous timing modes for Almost- Empty and Almost-Full flags ••••• Program programmable flags by either serial or parallel means ••••• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• JTAG port, provided for Boundary Scan function (BGA Only) ••••• Independent Read and Write Clocks (permit reading and writing simultaneously) ••••• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball Grid Array (BGA) (with additional features) ••••• Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293)family ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available ••••• Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM *Available on the BGA package only. |
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