9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

32,768 x 18 and 65,536 x 18

Figure 4. Programmable Flag Offset Programming Sequence

Figure 3. Offset Register Location and Default Values

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

WCLK

RCLK

X

X

XX

X

X

XX

4512 drw 07

LD

0

0

X

1

1

1

0

WEN

0

1

1

0

X

1

1

REN

1

0

1

X

0

1

1

X

SEN

1

1

1

X

X

X

0

72V275

72V285

Parallel write to registers:

Empty Offset

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

No Operation

Write Memory

Read Memory

No Operation

Serial shift into registers:

30 bits for the 72V275

32 bits for the 72V285

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

EMPTY OFFSET REGISTER

17

0

007FH if

LD is LOW at Master Reset,

03FFH if

LD is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

007FH if

LD is LOW at Master Reset,

03FFH if

LD is HIGH at Master Reset

14

72V275 (32,768 x 18_BIT)

15

14

15

EMPTY OFFSET REGISTER

17

0

007FH if

LD is LOW at Master Reset,

03FFH if

LD is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

007FH if

LD is LOW at Master Reset,

03FFH if

LD is HIGH at Master Reset

15

72V285 (65,536 x 18_BIT)

4512 drw 06

16

15

16