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72V2101L10PFG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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72V2101L10PFG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 27 page  JULY 2014 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 262,144 x 9 524,288 x 9 IDT72V2101 IDT72V2111 DSC-4669/5 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 © 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. FEATURES: ••••• Choose among the following memory organizations: IDT72V2101 ⎯ ⎯ ⎯ ⎯ ⎯ 262,144 x 9 IDT72V2111 ⎯ ⎯ ⎯ ⎯ ⎯ 524,288 x 9 • Pin-compatible with the IDT72V261/72V271 and the IDT72V281/ 72V291 SuperSync FIFOs • 10ns read/write cycle time (6.5ns access time) • Fixed, low first word data latency time • 5V input tolerant • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets • Program partial flags by either serial or parallel means • Select IDT Standard timing (using EFand FFflags) or First Word Fall Through timing (using OR and IR flags) • Output enable puts data outputs into high impedance state • Easily expandable in depth and width • Independent Read and Write clocks (permit reading and writing simultaneously) • Available in the 64-pin Thin Quad Flat Pack (TQFP) • High-performance submicron CMOS technology ••••• Industrial temperature range (–40°C to +85°C) is available ••••• Green parts available, see ordering information DESCRIPTION: The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These FIFOs offer numerous improvements over previous SuperSync FIFOs, includingthefollowing: • Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. • The period required by the retransmit operation is now fixed and short. • Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable clock cycle counting delay associated with the latency period found on previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.) SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu- nications,datacommunicationsandotherapplicationsthatneedtobufferlarge amountsofdata. FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 262,144 x 9 524,288 x 9 FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0 -D8 LD MRS REN RCLK OE Q0 -Q8 OFFSET REGISTER PRS FWFT/SI SEN RT 4669 drw 01 |
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