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72V2103L6PFG8 Datasheet(PDF) 7 Page - Integrated Device Technology

Part # 72V2103L6PFG8
Description  3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72V2103L6PFG8 Datasheet(HTML) 7 Page - Integrated Device Technology

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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
Symbol
Name
I/O
Description
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-45 and Figures 31-33.
PIN DESCRIPTION (BGA PACKAGE ONLY)
Symbol
Name
I/O
Description
ASYR(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
willselectAsynchronousoperation.
TCK(2)
JTAGClock
I
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAGTestData
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
Input
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
TDO(2)
JTAGTestData
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
Output
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
JTAG Mode
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
TRST(2)
JTAGReset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon
power-up. If the JTAG function is not used then this signal should to be tied to GND.
RM(1)
RetransmitTiming
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normallatencymode.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RT isusefultorereaddatafromthefirstphysicallocationoftheFIFO.
SEN
SerialEnable
I
SENenablesserialloadingofprogrammableflagoffsets.
WCLK/
WriteClock/
I
If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
WR
WriteStrobe
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the
FIFOonarisingedgeinanAsynchronousmanner,(WENshouldbetiedtoitsactivestate).Asynchronousoperation
of the WCLK/WR input is only available in the BGA package.
WEN
WriteEnable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
VCC
+3.3V Supply
I
These are VCC supply inputs and must be connected to the 3.3V supply rail.
NOTE:
1. Inputs should not change state after Master Reset.


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