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72V36100L6PFGI Datasheet(PDF) 5 Page - Integrated Device Technology |
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72V36100L6PFGI Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 48 page 5 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 BM IW OW Write Port Width Read Port Width L L L x36 x36 H L L x36 x18 H L H x36 x9 H H L x18 x36 H H H x9 x36 TABLE 1 — BUS-MATCHING CONFIGURATION MODES IfasynchronousPAE/PAFconfigurationisselected, the PAE isasserted LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW- to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transitionofRCLK. IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag Mode (PFM) pin. TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit operation by setting the read pointer to the first location of the memory array. Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zero latency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero latency retransmit operation is selected, the first data word to be retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK edgethatinitiatedtheretransmitbasedonRTbeingLOW. RefertoFigure11and12forRetransmitTimingwithnormallatency. Refer to Figure 13 and 14 for Zero Latency Retransmit Timing. Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected, thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See Figure 4 for Bus-Matching Byte Arrangement. TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser to select the parity bit in the word loaded into the parallel port (D0-Dn) when programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and D35 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits and D32, D33, D34 and D35 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. Interspersed Parity control only has an effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata written to and read from the FIFO. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and BoundaryScanArchitecture. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthepowerdownstate. TheIDT72V36100/72V36110arefabricatedusinghighspeedsubmicron CMOStechnology. NOTE: 1. Pin status during Master Reset. |
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