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IDT70V37L Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V37L Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC-4851/6 1 Functional Block Diagram ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ Separate upper-byte and lower-byte controls for multi- plexed bus and bus matching compatibility ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in a 100-pin TQFP ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V37L Active: 440mW (typ.) Standby: 660µW (typ.) ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70V37 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 3.3V 32K x 18 DUAL-PORT STATIC RAM IDT70V37L NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). I/O Control Address Decoder 32Kx18 MEMORY ARRAY 70V37 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ WL A14L A0L SEML INTL (2) BUSYL (1,2) LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/ WR A14R A0R SEMR INTR (2) BUSYR (1,2) LBR R/WR OER UBR M/ S (1) CE1L CE0R CE1R 4851 drw 01 CE1R CE1L I/O 9-17L I/O9-17R I/O 0-8L R/WL . 15 15 I/O0-8R |
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Similar Description - IDT70V37L_15 |
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