©2015 Integrated Device Technology, Inc.

JUNE 2015

DSC-4851/6

1

Functional Block Diagram

◆

◆

◆

◆

◆

◆

◆

◆

◆

◆

Busy and Interrupt Flags

◆

◆

◆

◆

◆

On-chip port arbitration logic

◆

◆

◆

◆

◆

Full on-chip hardware support of semaphore signaling

between ports

◆

◆

◆

◆

◆

Fully asynchronous operation from either port

◆

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

◆

◆

◆

◆

◆

LVTTL-compatible, single 3.3V (±0.3V) power supply

◆

◆

◆

◆

◆

Available in a 100-pin TQFP

◆

◆

◆

◆

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

◆

◆

◆

◆

Green parts available, see ordering information

Features

◆

◆

◆

◆

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

◆

◆

◆

◆

High-speed access

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

◆

◆

◆

◆

◆

Low-power operation

– IDT70V37L

Active: 440mW (typ.)

Standby: 660µW (typ.)

◆

◆

◆

◆

◆

Dual chip enables allow for depth expansion without

external logic

◆

◆

◆

◆

◆

IDT70V37 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

HIGH-SPEED 3.3V

32K x 18 DUAL-PORT

STATIC RAM

IDT70V37L

NOTES:

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

I/O

Control

Address

Decoder

32Kx18

MEMORY

ARRAY

70V37

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/

(2)

(1,2)

I/O

Control

Address

Decoder

R/

(2)

(1,2)

M/

S

(1)

4851 drw 01

.

15

15