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70V631S15BFGI8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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70V631S15BFGI8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 23 page 3 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. Due to the restricted number of pins, JTAG is not supported in the PK-128 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 69 68 67 66 65 91 71 A14L A15L A16L A17L IO9L IO9R VDDQL VSS IO10L IO10R VDDQR VSS IO11L IO11R IO12L IO12R VDD VDD VSS VSS IO13R IO13L IO14R IO14L IO15R IO15L VDDQL VSS IO16R IO16L VDDQR VSS IO17R IO17L A17R A16R A15R A14R A1R A0R OPTR IO0L IO0R VDDQR VSS IO1L IO1R VDDQL VSS IO2L IO2R IO3L IO3R IO4L IO4R VSS VSS VDD VDD IO5L IO5R VDDQR VSS IO7R IO7L VDDQL VSS NC IO8R IO8L VSS OPTL A0L A1L IO6R IO6L 70V631PRF PK-128(5) 128-Pin TQFP Top View(6) 5622 drw 02a . 09/30/03 Pin Configurations(1,2,3,4,7) (con't.) |
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