10

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS

Figure 4. Programmable Flag Offset Programming Sequence

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

WCLK

RCLK

X

X

XX

X

X

XX

4669 drw 07

LD

0

0

X

1

1

1

0

WEN

0

1

1

0

X

1

1

REN

1

0

1

X

0

1

1

X

SEN

1

1

1

X

X

X

0

No Operation

Write Memory

Read Memory

No Operation

IDT72V2101

IDT72V2111

Parallel write to registers:

Empty Offset (LSB)

Empty Offset (Mid-Byte)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (Mid-Byte)

Full Offset (MSB)

Parallel read from registers:

Empty Offset (LSB)

Empty Offset (Mid-Byte)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (Mid-Byte)

Full Offset (MSB)

Serial shift into registers:

36 bits for the 72V2101

38 bits for the 72V2111

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with FUll Offset (MSB)