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IDT70V07S Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT70V07S Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 19 page  IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) SEM 2943 drw 11 tAW tEW tSOP DATA0 VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATA VALID IN DATAOUT tDW tWP tDH tAS tSWRD tAOE tSOP Read Cycle Write Cycle A0-A2 OE VALID(2) SEM"A" 2943 drw 12 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE "B" (2) |
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