COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72V261LA/72V271LA

3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9

4

Symbol

Name

I/O

Description

Data Inputs

I

Data inputs for a 9-bit bus.

MRS

Master Reset

I

MRS

initializes the read and write pointers to zero and sets the output register to all zeroes.

During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of

two programmable flag default settings, and serial or parallel programming of the offset settings.

PRS

Partial Reset

I

PRS

initializes the read and write pointers to zero and sets the output register to all zeroes.

During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel),

and programmable flag settings are all retained.

RT

Retransmit

I

RT

asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to

LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming

method, existing timing mode or programmable flag settings. RT is useful to reread data from the first

physical location of the FIFO.

FWFT/SI

First Word Fall

I

During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,

Through/Serial In

this pin functions as a serial input for loading offset registers

WCLK

Write Clock

I

When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the

programmable registers for parallel programming, and when enabled by SEN, the rising edge of

WCLK writes one bit of data into the programmable register for serial programming.

WEN

Write Enable

I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

RCLK

Read Clock

I

When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets

from the programmable registers.

REN

Read Enable

I

REN

enables RCLK for reading data from the FIFO memory and offset registers.

OE

Output Enable

I

OE

SEN

Serial Enable

I

SEN

enables serial loading of programmable flag offsets.

LD

Load

I

During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023) and determines

the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to

and reading from the offset registers.

DC

Don't Care

I

FF

/IR

Full Flag/

O

In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO

Input Ready

memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there

is space available for writing to the FIFO memory.

EF

/OR

Empty Flag/

O

In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO

Output Ready

memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not

there is valid data available at the outputs.

PAF

Programmable

O

PAF

goes LOW if the number of words in the FIFO memory is more than total word capacity of

Almost-Full Flag

the FIFO minus the full offset value m, which is stored in the Full Offset register. There are two

possible default values for m: 127 or 1,023.

PAE

Programmable

O

PAE

goes LOW if the number of words in the FIFO memory is less than offset n, which is stored

Almost-Empty Flag

in the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values

for n can be programmed into the device.

HF

Half-Full Flag

O

HF

indicates whether the FIFO memory is more or less than half-full.

Data Outputs

O

Data outputs for a 9-bus

Power

+3.3 Volt power supply pins.

GND

Ground

Ground pins.

PIN DESCRIPTION