6.42

IDT71V30S/L

High-Speed 1K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

8

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

ADDRESS

OE

CE

R/

W

(2)

(4)

(4)

3741 drw 08

(6)

(7)

(7)

(7)

(3)

ADDRESS

CE

R/

W

3741 drw 09

(6)

(2)

(3)