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72V2103L15BCGI Datasheet(PDF) 11 Page - Integrated Device Technology |
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72V2103L15BCGI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 46 page 11 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns(1) Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load for tCLK = 10ns, 15 ns See Figure 2a Output Load for tCLK = 6ns, 7.5ns See Figure 2b & 2c AC TEST CONDITIONS Figure 2b. AC Test Load 6119 drw04a 50 Ω 1.5V I/O Z0 = 50 Ω 6119 drw04b 6 5 4 3 2 1 20 30 50 80 100 200 Capacitance (pF) Figure 2c. Lumped Capacitive Load, Typical Derating ACTESTLOADS-6ns,7.5nsSpeedGrades 6119 drw04 330 Ω 30pF* 510 Ω 3.3V D.U.T. Figure 2a. Output Load * Includes jig and scope capacitances. NOTE: 1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns. ACTESTLOADS-10ns,15nsSpeedGrades VIH OE VIL tOE & tOLZ VCC 2 VCC 2 100mV 100mV tOHZ 100mV 100mV Output Normally LOW Output Normally HIGH VOL VOH VCC 2 VCC 2 6119 drw04c Output Enable Output Disable OUTPUT ENABLE & DISABLE TIMING NOTE: 1. REN is HIGH. |
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