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70V07S35GGI8 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 70V07S35GGI8
Description  HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
Download  19 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70V07S35GGI8 Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
8
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
tRC
R/
W
CE
ADDR
tAA
OE
2943 drw 08
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
Symbol
Parameter
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Unit
Min.
Max.
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time
25
____
35
____
55
____
ns
tEW
Chip Enable to End-of-Write(3)
20
____
30
____
45
____
ns
tAW
Address Valid to End-of-Write
20
____
30
____
45
____
ns
tAS
Address Set-up Time(3)
0
____
0
____
0
____
ns
tWP
Write Pulse Width
20
____
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
20
____
30
____
ns
tHZ
Output High-Z Time(1,2)
____
15
____
20
____
25
ns
tDH
Data Hold Time(4)
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
____
15
____
20
____
25
ns
tOW
Output Active from End-of-Write(1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM
Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM
Flag Contention Window
5
____
5
____
5
____
ns
2943 tbl 12


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