 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
70V08L20PFG8 Datasheet(PDF) 10 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
70V08L20PFG8 Datasheet(HTML) 10 Page - Integrated Device Technology |
|
|
10 / 21 page  IDT70V08S/L High-Speed 3.3.V 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 3740 drw 08 tWC tAS tWR tDW tDH ADDRESS DATAIN R/ W tAW tEW (3) (2) (6) CE or SEM(9,10) Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. R/ W tWC tHZ tAW tWR tAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN CE or SEM (6) (4) (4) (3) 3740 drw 07 (7) (7) (9,10) |
Similar Part No. - 70V08L20PFG8 |
|
Similar Description - 70V08L20PFG8 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
